Programmable delay circuit and method with dummy circuit compensation

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United States of America Patent

PATENT NO 6242959
SERIAL NO

09453148

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Abstract

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One or more main programmed delay circuits (PDCs) are compensated to provide constant delays despite variations in environmental factors, such as temperature and power supply, by means of a dummy PDC that emulates the main PDCs in environmental sensitivity. While the main PDCs have dynamically changing programmed inputs, the dummy PDC has a constant programmed input. Changes in the dummy PDC's delay due to environmental changes are monitored and a correction signal is applied to the dummy PDC to maintain its delay substantially constant, with the same correction provided to the main PDCs to correct for the same changes in the delay of these circuits. The dummy PDC is preferably initially calibrated so that its fixed delay period coincides with an integer number of clock periods. Both the main and dummy PDCs preferably produce respective delays equal to the linear sum of a programmed delay and their correction delays.

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Patent Owner(s)

Patent OwnerAddress
ANALOG DEVICES INCONE ANALOG WAY WILMINGTON MA 01887

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Stern, Kenneth J Newton, MA 9 174

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