Multistage interconnect network uses a master processor to perform dynamic configuration for all switch nodes based on a predetermined topology
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United States of America Patent
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Jun 5, 2001
Issued Date -
N/A
app pub date -
Nov 10, 1998
filing date -
May 1, 1991
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Expired
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Abstract
A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 .vertline.log.sub.b N.vertline. stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and .vertline.log.sub.b N.vertline. indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
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