Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe

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United States of America Patent

PATENT NO 6243781
SERIAL NO

09205051

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Abstract

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In a bus resource having an outbound pipe for processing both non-posted and posted transactions in a FIFO manner, a rejected non-posted transaction at the head of the outbound pipe is moved aside and into an auxiliary buffer to avoid a potential blockage of the outbound pipe. The auxiliary buffer is for holding transaction information and return data of the rejected non-posted transaction. The rejected transaction is eventually completed from the auxiliary buffer as determined by an arbiter.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA MA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bogin, Zohar Folsom, CA 72 1639
Gadagkar, Ashish Sunnyvale, CA 3 43
Gandhi, Wishwesh Folsom, CA 13 116
Lent, David D Placerville, CA 8 92
Trieu, Tuong Folsom, CA 11 172

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