Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry
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United States of America Patent
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Jun 5, 2001
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N/A
app pub date -
Mar 31, 1998
filing date -
Mar 31, 1998
priority date (Note) -
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Abstract
A method and apparatus for computing a Packed Absolute Differences. According to one such method and apparatus, a third packed data having a third plurality of elements and the plurality of sign bits is produced, each of the third plurality of elements and the plurality of sign bits being computed by subtracting one of a first plurality of elements of a first packed data from a corresponding one of a second plurality of elements of a second packed data. The third plurality of elements and the plurality of sign bits are stored. A fourth packed data having a fourth plurality of elements is produced, each of the fourth plurality of elements being computed by subtracting one of the third plurality of elements from the corresponding one of an at least one element, if the corresponding one of a plurality of sign bits is in a first state; and adding one of the third plurality of elements from the corresponding one of the at least one element, if the corresponding one of the plurality of sign bits is in a second state.
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