Memory outputting both data and timing signal with output data and timing signal being aligned with each other
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United States of America Patent
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Jun 12, 2001
Grant Date -
N/A
app pub date -
Sep 21, 1999
filing date -
Jan 21, 1994
priority date (Note) -
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Abstract
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.
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