Method of fabricating an ONO dielectric by nitridation for MNOS memory cells
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 19, 2001
Grant Date -
N/A
app pub date -
Oct 25, 1999
filing date -
Oct 25, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide layer in an ambient atmosphere of at least one of nitric oxide, nitrous oxide and ammonia. In this regard, nitrogen is incorporated into the first silicon oxide layer which leads to a better performance and a higher quality of the ONO structure. A silicon nitride layer is formed to overlie the first silicon oxide layer; and a second layer of silicon oxide is formed to overlie the silicon nitride layer to complete the ONO structure.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully