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Abstract

A method of forming a self-aligned contact in a semiconductor device comprising a semiconductor substrate and a gate line. The method comprises the steps of forming a conductive layer on an overall surface of the semiconductor substrate including the gate line, planarization-etching the conductive layer down to the gate line, and etching the conductive layer to form the contact, the etching performed at least until the contact is electrically separated from other portions of the conductive layer. The method may reduce or eliminate pad-to-gate electrode shorts by preventing exposure during etching of the gate electrode, reduce or eliminate pad-to-pad bridging by preventing generation of void regions, and reduce contact resistance by securing enough contact area between a pad and an active region in spite of misalignment of a photoresist pattern.

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First Claim