Dual bus processing apparatus wherein second control means request access of first data bus from first control means while occupying second data bus
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United States of America Patent
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Jun 19, 2001
Grant Date -
N/A
app pub date -
Dec 22, 1998
filing date -
Dec 22, 1997
priority date (Note) -
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Abstract
In an information processing apparatus equipped with a CPU, an operating rate of this CPU is increased so as to increase a throughput of this entire information processing apparatus. The information processing apparatus is arranged by first and second internal buses independently provided from each other, an internal memory connected to the first internal bus, and a timer 25 connected to the second internal bus. Furthermore, this information processing apparatus is arranged by an A/D converter, first/second serial interfaces, the CPU, and a DMAC (direct memory access controller). Both the CPU and the DMAC control data input/output operations in the internal memory and the timer while occupying at least one of these fist/second data buses. The DMAC supplies a request signal to such a CPU for controlling the data input/output operation of the internal memory while occupying at least one of the first/second internal buses, and also controls the data input/output operations in the internal memory in response to an acknowledge signal supplied from the CPU while occupying either one or both the first/second internal buses.
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