Method and apparatus for submicron IC design using edge fragment tagging to correct edge placement distortion
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United States of America Patent
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Jun 19, 2001
Grant Date -
N/A
app pub date -
Apr 30, 1999
filing date -
Apr 30, 1999
priority date (Note) -
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Abstract
The present invention beneficially provides an improved method and apparatus for designing submicron integrated circuits. A tag identifier is provided to an integrated circuit (IC) design. The tag identifier defines properties for edge fragments in the IC design having edge placement distortion due to the proximity of neighboring features. Edge fragments are tagged if they have the properties defined by the tag identifier. Arbitrary assist features are introduced for each tagged edge fragment. Model-based optical and process correction (OPC) is performed on the tagged edge fragments and the corresponding assist features.
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