Importance

Loading Importance Indicators...

Abstract

A multi-port bridge includes a plurality of ports interconnected by a communication bus. A memory device, utilized for temporarily storing packets to be bridged by the multi-port bridge, is accessed by each port via the communication bus. A memory pointer for each packet to be transmitted by a port is stored in a memory pointer buffer within the port. The memory pointer includes an address assigned to the packet in the memory device. Each port includes: a first finite state machine (transmit FSM) which controls retrieving packets from the memory device and transmitting the packets to the network segment associated with the port; a second FSM (memory pointer FSM) which controls receiving memory pointers from the communication bus and storing the memory pointers in the memory pointer buffer; and a third FSM (receive FSM) which controls receiving packets from the network segment associated with the port and storing the packets in the memory device. Each FSM requires a set of registers, including a counter for keeping track of the current state of the FSM and registers for storing parameters utilized by the FSM. At any time, none, one, two or all of the FSMs in a port can be active. At least one register is identified that is used only in certain states in each of the FSMs such that no more than one FSM requires use of this register at the same time. Accordingly, each of the three FSMs share at least one register.

Loading the Abstract Image...

First Claim