Method and apparatus for bridging a plurality of buses and handling of an exception event to provide bus isolation
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United States of America Patent
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Jun 26, 2001
Grant Date -
N/A
app pub date -
Jun 28, 1999
filing date -
Jun 28, 1999
priority date (Note) -
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Abstract
A bus bridge coupled between two bridges providing bus exception event isolation and address/data translation. In one embodiment the bus bridge includes two direct memory access (DMA) engines and a first-in-first-out (FIFO) buffer interface between the DMA engines to provide the bus exception isolation. The DMA engines and FIFOs also enable a packet based message passing architecture, which eliminates the need for address translation and also handles data reordering.
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