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Abstract

A timing generator capable of setting data indicating that a timing signal is to be generated in the next cycle, even in the case of generating test pattern signals in multiple way system is provided. In each of clock data processing circuits of N timing generators, N being an integer of 2 or greater than 2, are provided a multiplier for multiplying by N a value of period data read out of period data memory of the associated clock data processing circuit, a subtracter for performing a subtraction between the period data multiplied by N by the multiplier and clock data supplied from a main controller, and means for providing, only in the case that N or more period data are in succession, the period of each of the period data being a constant, a control signal to the associated clock data processing circuit, the control signal enabling a subtraction value outputted from an output terminal of the associated subtracter and a next flag outputted from a carry signal output terminal of the associated subtracter when a value of the clock data is greater than that of the period data multiplied by N to be stored in the memory of the associated clock generator, the next flag representing that a clock is to be generated in the next cycle.

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First Claim