High tunability CMOS delay element
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United States of America Patent
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Jul 3, 2001
Grant Date -
N/A
app pub date -
Nov 17, 1999
filing date -
Nov 26, 1998
priority date (Note) -
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Abstract
The delay element consists of a differential amplifier (M15, M8, M2, M6, M5) in which the load transistors (M2, M5) are associated to respective gate biasing transistors (M21, M22) connected in a source follower configuration, and to feedback transistors (M3, M4), which implement a negative impedance in parallel to a positive impedance represented by each of the load transistors (M2, M5). The modulation of the delay is achieved by modulating the bias currents of the load transistors (M2, M5), the feedback transistors (M3. M4) and the gate biasing transistors (M21, M22).
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