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Abstract

A structure and method for implementing an EEPROM using 2-bit non-volatile memory cells. Each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The memory cells are arranged in one or more rows, with a word line coupling the gates of all of the memory cells in each row. Diffusion bit lines couple the first charge trapping region of each memory cell with the second charge trapping region of an adjacent memory cell. When the first charge trapping region of a memory cell is erased, the second charge trapping region of the adjacent memory cell is incidentally erased. This incidental erasure is effectively avoided by: (1) reading the bit stored in the second charge trapping region, (2) writing this bit to a storage device, (3) performing the erase operation, and then (4) restoring the bit from the storage device to the second charge trapping region of the adjacent memory cell. If an erase operation results in the incidental erasure of additional bits (as will occur when more than one row of memory cells is coupled to a single diffusion bit line), then all of the bits that would be incidentally erased are written to the storage device before the erase operation, and are restored to the array after the erase operation. The incidental erasure can also be rendered moot by using only one charge trapping region of each memory cell.

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