Memory device with support for unaligned access
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Jul 3, 2001
Grant Date -
N/A
app pub date -
Feb 18, 2000
filing date -
Feb 18, 2000
priority date (Note) -
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Abstract
An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.
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