Importance

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Abstract

A method and apparatus for reliable interrupt reception over a buffered bus utilizes a mailbox register to receive interrupt request information sent after a data write transaction. The data is sent from an initiating peripheral device over the buffered bus to arrive with an arbitrary delay at the host memory. After completing the sending phase for the data the initiating peripheral device sends a mailbox register data block containing an interrupt request to a mailbox register associated with the host processor. Because the mailbox register data block will necessarily arrive after the receipt of the actual data in the host memory because it is following the actual data through the same buffered bus, the interrupt will be properly sequenced with the receipt of data.

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First Claim