Importance

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Abstract

A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit or miss occurs during a given data or instruction access. Memory area priority protection is achieved by employing a gateway instruction which includes a gateway register pointer and the priority level of the instruction. The gateway register holds a pointer to a specific entry point within a high priority area within memory at which the lower priority gateway instruction may enter it.

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First Claim