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Abstract

Delay circuitry includes a phase-locked loop or PLL for comparing the phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to the phase difference between the phases of the reference clock and other clock, for generating the other clock using at least a plurality of delay elements connected into a loop, a time delay provided by each of the plurality of delay elements being controlled by the control signal, and for changing the value of the control signal so that the other clock is made to be in phase with the reference clock. The delay circuitry further includes a register for storing information to set a certain time delay, and a delay unit including a plurality of delay elements each of which provides an input with a time delay that is controlled by the control signal from the PLL, for determining the number of delay elements through which an input signal is to be passed according to the information stored in the register, so as to provide the input signal with the predetermined time delay.

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First Claim