Importance

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Abstract

A data and clock recovery phase locked loop circuit comprises a data transition detector block to detect transitions of random input data and to produce a window signal. A delay block delays the random input data to produce delayed random input data. A phase comparator block is connected to the delay block and compares phase of the delayed random input data with phase of a feedback signal to produce a phase compared signal. A charge pump block is connected to the phase comparator block and produces output voltage in response to the phase compared signal. A filter block is connected to the charge pump block to filter the output voltage into DC voltage. A voltage controlled oscillator is connected to the filter block to generate the clock signal which has a frequency depending on the DC voltage. A multiplexer block is connected to the voltage controlled oscillator, the data transition detector block, and the phase comparator block and selects one from a predetermined logical level and the clock signal to supply a selected signal to the phase comparator block as the feedback signal.

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