Apparatus and method for high performance implementation of system calls
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United States of America Patent
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Jul 10, 2001
Grant Date -
N/A
app pub date -
Mar 1, 1995
filing date -
Mar 1, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
A method and apparatus for bypassing multiple pre-tests and post-tests during a system call when those tests are known to be inapplicable. One or more slow path flags are checked during a system call or TRAP. If the slow path flag is clear, execution follows a fast instruction path, resulting in faster execution for the system call or TRAP. Otherwise execution follows a slow instruction path. The slow path flags are set, cleared, and checked at appropriate times. The invention improves the execution time of a thread in a software process and may be used in a data processing system employing multiple threads. Each thread in the data processing system has its own set of slow path flags. The invention can set, clear and check the slow path flags of each thread independently, in subsets of threads, or in all threads.
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