Importance

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Abstract

A controller circuit (100) includes an aliasing circuit (261) for efficiently transferring a set of peripheral data words between a microprocessor (130) and a serial peripheral device (140) that has a first in and first out (FIFO) register (220). The aliasing circuit aliases sequential addresses within a predetermined range of addresses that are generated by the microprocessor during a load multiple or store multiple command, wherein each of the sequential addresses is associated with one peripheral data word of the set of peripheral data words. The serial peripheral device comprises the FIFO register and a data bus register (210) for transferring each peripheral data word between the FIFO register and the microprocessor. A central processing unit (CPU) (125) of the microprocessor uses a CPU word that is not necessarily the same length as the peripheral data word.

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First Claim