Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
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United States of America Patent
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Jul 17, 2001
Grant Date -
N/A
app pub date -
Jun 23, 1999
filing date -
Jun 23, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility., achieve facility of wiring design, and reduce production cost. The present invention forms a X-Y reference wiring grid using wirings of a total of M (M.gtoreq.2) layers in which an n-th (n.gtoreq.2) layer wiring intersects orthogonally with a (n-1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the(m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of 2 times of that of wiring in the reference wiring grid, and also wiring widths of 2 times of that of wiring in the reference wiring layer.
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