US Patent No: 6,262,921

Number of patents in Portfolio can not be more than 2000

Delay-locked loop with binary-coupled capacitor

1 Status Updates

Stats

ATTORNEY / AGENT: (SPONSORED)
 

Importance

Loading Importance Indicators... loading....

Abstract

A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.

Loading the Abstract Image... loading....

First Claim

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
MOSAID TECHNOLOGIES INCORPORATEDOTTAWA1227

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Manning, Troy A Meridian, ID 229 4844

Cited Art

Patent Info (Count) # Cites Year
 
RAMBUS INC. (20)
5,243,703 Apparatus for synchronously generating clock signals in a data processing system 354 1992
5,473,575 Integrated circuit I/O using a high performance bus interface 110 1992
5,355,391 High speed bus system 307 1992
5,390,308 Method and apparatus for address mapping of dynamic random access memory 156 1992
5,254,883 Electrical current source circuitry for a bus 336 1992
5,268,639 Testing timing parameters of high speed integrated circuit devices 115 1992
5,337,285 Method and apparatus for power control in devices 138 1993
5,451,898 Bias circuit and differential amplifier having stabilized output swing 127 1993
5,432,823 Method and circuitry for minimizing clock-data skew in a bus system 330 1994
5,430,676 Dynamic random access memory system 113 1994
5,513,327 Integrated circuit I/O using a high performance bus interface 198 1994
5,485,490 Method and circuitry for clock synchronization 234 1994
5,446,696 Method and apparatus for implementing refresh in a synchronous DRAM system 120 1994
5,578,940 Modular bus with single or double parallel termination 151 1995
5,488,321 Static high speed comparator 103 1995
5,621,340 Differential comparator for amplifying small swing signals to a full swing output 104 1995
5,614,855 Delay-locked loop 274 1995
5,657,481 Memory device with a phase locked loop circuitry 110 1996
6,101,152 Method of operating a synchronous memory device 115 1998
6,067,592 System having a synchronous memory device 59 1999
 
MICRON TECHNOLOGY, INC. (17)
4,958,088 Low power three-stage CMOS input buffer with controlled switching 113 1989
5,128,563 CMOS bootstrapped output driver method and circuit 111 1990
5,150,186 CMOS output pull-up driver 120 1991
5,128,560 Boosted supply output driver circuit for driving an all N-channel output stage 202 1991
5,278,460 Voltage compensating CMOS input buffer 132 1992
5,274,276 Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit 143 1992
5,311,481 Wordline driver circuit having a directly gated pull-down device 111 1992
5,347,179 Inverting output driver circuit for reducing electron injection into the substrate 111 1993
5,506,814 Video random access memory device and method implementing independent two WE nibble control 98 1993
5,361,002 Voltage compensating CMOS input buffer 125 1993
5,400,283 RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver 98 1993
5,555,429 Multiport RAM based multiprocessor 50 1995
5,508,638 Low current redundancy fuse assembly 115 1995
5,578,941 Voltage compensating CMOS input buffer circuit 107 1995
5,657,289 Expandable data width SAM for a multiport RAM 55 1995
5,805,931 Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols 51 1996
5,574,698 Ram row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver 99 1996
 
ROUND ROCK RESEARCH, LLC (16)
5,276,642 Method for performing a split read/write operation in a dynamic random access memory 103 1991
5,544,124 Optimization circuitry and control for a synchronous memory device with programmable latency period 109 1995
5,636,173 Auto-precharge during bank selection 169 1995
5,692,165 Memory controller with low skew control signal 162 1995
5,627,791 Multiple bank memory with auto refresh to specified bank 188 1996
5,852,378 Low-skew differential signal converter 105 1997
5,920,518 Synchronous clock generator including delay-locked loop 112 1997
5,940,608 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal 110 1997
5,953,284 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 82 1997
6,011,732 Synchronous clock generator including a compound delay-locked loop 201 1997
5,926,047 Synchronous clock generator including a delay-locked loop signal loss detector 67 1997
5,940,609 Synchronous clock generator including a false lock detector 97 1997
6,101,197 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 134 1997
6,016,282 Clock vernier adjustment 216 1998
6,029,250 Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same 319 1998
6,026,050 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 146 1999
 
TEXAS INSTRUMENTS INCORPORATED (7)
4,638,451 Microprocessor system with programmable interface 69 1983
4,687,951 Fuse link for varying chip operating parameters 79 1984
5,220,208 Circuitry and method for controlling current in an electronic circuit 107 1991
5,430,408 Transmission gate circuit 57 1994
5,544,203 Fine resolution digital delay line with coarse and fine adjustment stages 165 1994
5,576,645 Sample and hold flip-flop for CMOS logic 94 1995
5,841,707 Apparatus and method for a programmable interval timing generator in a semiconductor memory 70 1996
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (6)
5,020,023 Automatic vernier synchronization of skewed data streams 68 1989
5,272,729 Clock signal latency elimination network 98 1991
5,557,224 Apparatus and method for generating a phase-controlled clock signal 50 1994
5,577,236 Memory controller for reading data from synchronous RAM 150 1994
5,568,075 Timing signal generator 62 1995
5,712,580 Linear phase detector for half-speed quadrature clocking architecture 77 1996
 
MITSUBISHI DENKI KABUSHIKI KAISHA (6)
4,953,128 Variable delay circuit for delaying input data 131 1987
5,313,431 Multiport semiconductor memory device 75 1992
5,552,727 Digital phase locked loop circuit 81 1994
5,568,077 Latch circuit 89 1995
5,668,774 Dynamic semiconductor memory device having fast operation mode and operating with low current consumption 65 1996
5,708,611 Synchronous semiconductor memory device 86 1997
 
INTEL CORPORATION (5)
5,410,263 Delay line loop for on-chip clock synthesis with zero skew and 50% duty cycle 98 1993
5,489,864 Delay interpolation circuitry 75 1995
5,621,690 Nonvolatile memory blocking architecture and redundancy 136 1995
5,652,530 Method and apparatus for reducing clock-data skew by clock shifting 70 1995
5,621,739 Method and apparatus for buffer self-test and characterization 111 1996
 
MOTOROLA, INC. (5)
4,508,983 MOS Analog switch driven by complementary, minimally skewed clock signals 58 1983
4,573,017 Unitary phase and frequency adjust network for a multiple frequency digital phase locked loop 62 1984
4,893,087 Low voltage and low power frequency synthesizer 94 1988
5,256,989 Lock detection for a phase lock loop 75 1991
5,428,317 Phase locked loop with low power feedback path and method of operation 53 1994
 
AVAGO TECHNOLOGIES GENERAL IP PTE. LTD. (3)
5,283,631 Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations 107 1991
5,473,639 Clock recovery apparatus with means for sensing an out of lock condition 66 1993
5,581,197 Method of programming a desired source resistance for a driver stage 113 1995
 
CREDENCE SYSTEMS CORPORATION (3)
4,902,986 Phased locked loop to provide precise frequency and phase tracking of two signals 85 1989
5,075,569 Output device circuit and method to minimize impedance fluctuations during crossover 77 1990
6,105,157 Salphasic timing calibration system for an integrated circuit tester 60 1998
 
ELPIDA MEMORY, INC. (3)
5,638,335 Semiconductor device 89 1996
5,781,499 Semiconductor memory device 53 1996
5,768,177 Controlled delay circuit for use in synchronized semiconductor memory 61 1997
 
KABUSHIKI KAISHA TOSHIBA (3)
5,233,564 Multiport memory with test signal generating circuit controlling data transfer from RAM port to SAM port 48 1991
5,675,274 Semiconductor clock signal generation circuit 69 1995
5,926,436 Semiconductor memory device 51 1998
 
OKI SEMICONDUCTOR CO., LTD. (3)
5,311,483 Synchronous type semiconductor memory 154 1993
5,646,904 Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed 74 1995
5,751,665 Clock distributing circuit 92 1996
 
RENESAS ELECTRONICS CORPORATION (3)
5,420,544 Semiconductor integrated circuit, method of designing the same and method of manufacturing the same 135 1993
5,444,667 Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals 114 1994
5,636,163 Random access memory with a plurality amplifier groups for reading and writing in normal and test modes 92 1996
 
ADVANCED MICRO DEVICES, INC. (2)
5,233,314 Integrated charge-pump phase-locked loop circuit 123 1992
5,964,884 Self-timed pulse control circuit 57 1997
 
FREESCALE SEMICONDUCTOR, INC. (2)
5,402,389 Synchronous memory having parallel output data paths 96 1994
5,440,514 Write control for a memory using a delay locked loop 117 1994
 
FUJITSU SEMICONDUCTOR LIMITED (2)
5,668,763 Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks 108 1996
5,740,123 Semiconductor integrated circuit for changing pulse width according to frequency of external signal 72 1997
 
GENERAL PATENT CORPORATION (2)
4,603,320 Connector interface 86 1983
4,972,470 Programmable connector 206 1987
 
NEC CORPORATION (2)
5,572,557 Semiconductor integrated circuit device including PLL circuit 63 1994
5,631,872 Low power consumption semiconductor dynamic random access memory device by reusing residual electric charge on bit line pairs 92 1996
 
PARADYNE CORPORATION (2)
5,898,674 System and method for performing non-disruptive diagnostics through a frame relay circuit 74 1997
6,038,219 User-configurable frame relay network 102 1997
 
SGS-THOMSON MICROELECTRONICS, INC. (2)
5,428,311 Fuse circuitry to control the propagation delay of an IC 109 1993
5,579,326 Method and apparatus for programming signal timing 62 1994
 
UNISYS CORPORATION (2)
5,289,580 Programmable multiple I/O interface controller 148 1991
5,594,690 Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse generator 62 1995
 
VLSI TECHNOLOGY, INC. (2)
5,416,909 Input/output controller circuit using a single transceiver to serve multiple input/output ports and method therefor 57 1992
5,557,781 Combination asynchronous cache system and automatic clock tuning device and method therefor 50 1993
 
ADVANTEST (SINGAPORE) PTE LTD (1)
5,589,788 Timing adjustment circuit 109 1995
 
ADVANTEST CORPORATION (1)
5,440,260 Variable delay circuit 99 1994
 
APPLE INC. (1)
5,295,164 Apparatus for providing a system clock locked to an external clock over a wide range of frequencies 105 1991
 
AT&T BELL LABORATORIES (1)
5,194,765 Digitally controlled element sizing 198 1991
 
AT&T IPM CORP. (1)
5,448,193 Normalization of apparent propagation delay 79 1994
 
BELL COMMUNICATIONS RESEARCH, INC. (1)
4,773,085 Phase and frequency detector circuits 102 1987
 
BELL TELEPHONE LABORATORIES, INCORPORATED (1)
4,514,647 Chipset synchronization arrangement 74 1983
 
BURR-BROWN CORPORATION (1)
5,694,065 Switching control circuitry for low noise CMOS inverter 111 1995
 
CIENA CORPORATION (1)
5,719,508 Loss of lock detector for master timing generator 54 1996
 
DDK LTD. (1)
5,087,828 Timing circuit for single line serial data 71 1991
 
DIGITAL EQUIPMENT CORPORATION (1)
5,539,345 Phase detector apparatus 75 1992
 
ELUMINANT TECHNOLOGIES, INC. (1)
5,473,274 Local clock generator 71 1992
 
ELXSI CORPORATION, A DE CORP. (1)
4,481,625 High speed data bus system 170 1981
 
FRANCE TELECOM (1)
5,416,436 Method for time delaying a signal and corresponding delay circuit 72 1993
 
GENERAL INSTRUMENT CORPORATION (1)
5,315,388 Multiple serial access memory for use in feedback systems such as motion compensated television 96 1991
 
GLOBALFOUNDRIES INC. (1)
5,239,206 Synchronous circuit with clock skew compensating function and circuits utilizing same 118 1992
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
5,408,640 Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes 62 1992
 
HITACHI VLSI ENGINEERING CORP. (1)
4,984,204 High speed sensor system using a level shift circuit 141 1989
 
HITACHI, LTD. (1)
5,281,865 Flip-flop circuit 121 1991
 
INFINEON TECHNOLOGIES AG (1)
5,321,368 Synchronized, digital sequential circuit 95 1993
 
INTELLECTUAL PROPERTIES I KFT. (1)
5,619,473 Semiconductor memory device with dual address memory read amplifiers 100 1995
 
INTELLECTUAL VENTURES II LLC (1)
5,636,174 Fast cycle time-low latency dynamic random access memories and systems and methods using the same 138 1996
 
JAZIO, INC. (1)
6,160,423 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 117 1998
 
LG SEMICON CO., LTD. (1)
5,438,545 Data output buffer of semiconductor memory device for preventing noises 98 1994
 
LOCKHEED MARTIN CORPORATION (1)
5,122,690 Interface circuits including driver circuits with switching noise reduction 164 1990
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
5,179,298 CMOS buffer circuit which is not influenced by bounce noise 118 1991
 
MICROCHIP TECHNOLOGY INCORPORATED (1)
5,889,829 Phase locked loop with improved lock time and stability 55 1997
 
MILAN JANKOVIC (1)
5,134,311 Self-adjusting impedance matching driver 291 1990
 
MINNESOTA MINING AND MANUFACTURING COMPANY (1)
4,600,895 Precision phase synchronization of free-running oscillator output signal to reference signal 72 1985
 
MOSYS, INC. (1)
5,498,990 Reduced CMOS-swing clamping circuit for bus lines 129 1995
 
MOTOROLA MOBILITY LLC (1)
5,822,314 Communications system and method of operation 64 1996
 
MYERS, GLEN A. (1)
5,038,115 Method and apparatus for frequency independent phase tracking of input signals in receiving systems and the like 91 1990
 
NEC ELECTRONICS CORPORATION (1)
5,563,546 Selector circuit selecting and outputting voltage applied to one of first and second terminal in response to voltage level applied to first terminal 63 1994
 
NEC ELECTRONICS, INC. (1)
5,666,322 Phase-locked loop timing controller in an integrated circuit memory 127 1995
 
NIPPONDENSO CO., LTD. (1)
5,465,076 Programmable delay line programmable delay circuit and digital controlled oscillator 110 1993
 
NXP B.V. (1)
4,789,796 Output buffer having sequentially-switched output 118 1986
 
RCA CORPORATION (1)
4,404,474 Active load pulse generating circuit 109 1981
 
SAMSUNG ELECTRONICS CO., LTD. (1)
5,812,619 Digital phase lock loop and system for digital clock recovery 71 1996
 
SARNOFF CORPORATION (1)
5,497,127 Wide frequency range CMOS relaxation oscillator with variable hysteresis 99 1994
 
SCHLUMBERGER SYSTEMS AND SERVICES, INC. (1)
4,511,846 Deskewing time-critical signals in automatic test equipment 69 1982
 
SEIKO NPC CORPORATION (1)
5,789,947 Phase comparator 65 1996
 
SGS-THOMSON MICROELECTRONICS LIMITED (1)
5,627,780 Testing a non-volatile memory 96 1995
 
SGS-THOMSON MICROELECTRONICS S.R.L. (1)
5,663,921 Internal timing method and circuit for programmable memories 53 1995
 
SIEMENS MEDICAL SOLUTIONS USA, INC. (1)
5,767,715 Method and apparatus for generating timing pulses accurately skewed relative to clock 59 1995
 
SILICON GRAPHICS INTERNATIONAL, CORP. (1)
5,790,612 System and method to reduce jitter in digital delay-locked loops 92 1996
 
SLORAM, INC. (1)
5,917,760 De-skewing data signals in a memory system 182 1997
 
SONY CORPORATION (1)
5,590,073 Random access memory having flash memory 113 1994
 
SONY ELECTRONICS INC. (1)
5,457,407 Binary weighted reference circuit for a variable impedance output buffer 157 1994
 
SPX CORPORATION (1)
5,532,714 Method and apparatus for combining video images on a pixel basis 52 1994
 
ST. CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC. (1)
5,086,500 Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits 97 1989
 
STMICROELECTRONICS, INC. (1)
5,367,649 Programmable controller 49 1990
 
SYNOPSYS, INC. (1)
5,500,808 Apparatus and method for estimating time delays using unmapped combinational logic networks 62 1995
 
TRANSCRYPT INTERNATIONAL, INC. (1)
5,784,422 Apparatus and method for accurate synchronization with inbound data packets at relatively low sampling rates 66 1996
 
VTC C-MOS INCORPORATED (1)
4,638,187 CMOS output buffer providing high drive current with minimum output signal distortion 209 1985
 
WESTERN DIGITAL TECHNOLOGIES, INC. (1)
5,212,601 Disk drive data synchronizer with window shift synthesis 64 1991
 
WINBOND ELECTRONICS CORP. (1)
5,257,294 Phase-locked loop circuit and method 103 1990
 
XEROX CORPORATION (1)
5,223,755 Extended frequency range variable delay locked loop for clock synchronization 154 1990
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (2)
5,165,045 Method and apparatus for measuring displacement having parallel grating lines perpendicular to a displacement direction for diffracting a light beam 12 1991
5,347,177 System for interconnecting VLSI circuits with transmission line characteristics 139 1993

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (27)
6,912,680 Memory system with dynamic timing correction 34 1997
6,470,060 Method and apparatus for generating a phase dependent control signal 21 1999
6,959,016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 13 2000
6,954,097 Method and apparatus for generating a sequence of clock signals 7 2001
6,801,989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 53 2001
6,499,111 Apparatus for adjusting delay of a clock signal relative to a data signal 42 2001
6,477,675 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2001
6,662,304 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 125 2002
6,643,789 Computer system having memory device with adjustable data clocking using pass gates 17 2002
6,931,086 Method and apparatus for generating a phase dependent control signal 12 2002
7,016,451 Method and apparatus for generating a phase dependent control signal 4 2002
6,647,523 Method for generating expect data from a captured bit pattern, and memory device using same 12 2002
7,168,027 Dynamic synchronization of data capture on an optical or other high speed communications link 11 2003
7,085,975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 4 2003
7,159,092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 4 2003
7,193,910 Adjustable timing circuit of an integrated circuit 3 2004
7,415,404 Method and apparatus for generating a sequence of clock signals 3 2005
7,418,071 Method and apparatus for generating a phase dependent control signal 7 2005
7,130,227 Adjustable timing circuit of an integrated circuit 2 2005
7,373,575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2006
8,181,092 Dynamic synchronization of data capture on an optical or other high speed communications link 0 2006
7,889,593 Method and apparatus for generating a sequence of clock signals 0 2007
7,657,813 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2008
7,602,876 Method and apparatus for generating a phase dependent control signal 5 2008
8,107,580 Method and apparatus for generating a phase dependent control signal 1 2009
7,954,031 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 0 2009
8,433,023 Method and apparatus for generating a phase dependent control signal 0 2012
 
MICRON TECHNOLOGY, INC. (7)
6,618,283 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal 23 2001
6,611,475 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal 20 2002
6,812,753 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal 14 2002
6,759,882 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal 5 2002
7,234,070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 13 2003
7,137,024 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 0 2003
7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 5 2006
 
RAMBUS INC. (4)
7,668,276 Phase adjustment apparatus and method for a memory device signaling system 2 2002
6,920,540 Timing calibration apparatus and method for a memory device signaling system 24 2002
7,398,413 Memory device signaling system and method with independent timing calibration for parallel signal paths 1 2005
7,965,567 Phase adjustment apparatus and method for a memory device signaling system 1 2007
 
MOSAID TECHNOLOGIES INCORPORATED (3)
6,483,757 Delay-locked loop with binary-coupled capacitor 1 2001
6,490,224 Delay-locked loop with binary-coupled capacitor 9 2001
6,490,207 Delay-locked loop with binary-coupled capacitor 22 2001
 
658868 N.B. INC. (1)
6,593,786 Register controlled DLL reducing current consumption 16 2002
 
CIRRUS LOGIC, INC. (1)
6,445,330 Capacitively coupled references for isolated analog-to-digital converter systems 5 2001
 
ELPIDA MEMORY, INC. (1)
7,719,921 Duty detection circuit, DLL circuit using the same, semiconductor memory circuit, and data processing system 1 2008
 
NEC ELECTRONICS CORPORATION (1)
6,526,106 Synchronous circuit controller for controlling data transmission between asynchrous circuit 11 1998
 
SAMSUNG ELECTRONICS CO., LTD. (1)
7,710,818 Semiconductor memory device having low jitter source synchronous interface and clocking method thereof 0 2007

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
11.5 Year Payment $7400.00 $3700.00 $1850.00 Jan 17, 2013
Fee Large entity fee small entity fee micro entity fee
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00