Current mode logic gates for low-voltage high speed applications
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United States of America Patent
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Jul 24, 2001
Grant Date -
N/A
app pub date -
Sep 25, 2000
filing date -
Jul 13, 1998
priority date (Note) -
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Abstract
A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.
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