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Abstract

A receiver is provided, whereby bit error rate can be improved, while achieving savings in power consumption. The receiver comprises: a quadrature detector 12 for converting an intermediate frequency signal obtained on the basis of a reception signal to a base band signal; a comparator 16 for converting the base band signal to binary form after it has passed through a first LPF 14, which is an analogue filter; a second LPF (CIC filter) 18 for transmitting frequency components of the approximate square wave output by comparator 16 which are odd factors of the fundamental frequency of the signal; and a sampler 20 and comparator 24 which decode the output signal from the second LPF 18 in accordance with a clock reproduced by a clock reproducing circuit 22 on the basis of this output signal.

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First Claim