Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layer
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United States of America Patent
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Jul 31, 2001
Grant Date -
N/A
app pub date -
May 18, 1998
filing date -
May 18, 1998
priority date (Note) -
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Abstract
A method for forming a copper interconnect begins by depositing a barrier layer (48) within an in-laid region (18). An edge exclusion protection layer (50) is formed over the barrier layer (48), and this layer (50) is processed so that it only lies within the edge exclusion region (20) of the wafer. The layer (50) is removed from active area portions of the wafer so that contact resistance of copper interconnects is not affected. Wet surface processing is used to form a catalyst (64b) on the wafer surface to enable electroless copper plating within active areas of the wafer to form a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20). Electroplating is then used to thicken the copper material to form a copper layer (54) over the layer (52) wherein the in-laid copper interconnect is completed.
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