Low temperature process for multiple voltage devices
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United States of America Patent
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Jul 31, 2001
Grant Date -
N/A
app pub date -
Dec 18, 1998
filing date -
Dec 31, 1997
priority date (Note) -
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Abstract
A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface. Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30). The entire wafer (10) is exposed to a nitrogen ion containing plasma to form a nitrided layer (22). The photoresist (14) is removed, and the exposed portion of the oxide layer (12) is etched to the wafer (10) surface. Finally, an oxidation step forms a silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).
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