Core clock correction in a 2/n mode clocking scheme
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United States of America Patent
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Jul 31, 2001
Issued Date -
N/A
app pub date -
May 31, 2000
filing date -
Dec 29, 1995
priority date (Note) -
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Abstract
A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
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