Priority encoder/read only memory (ROM) combination
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 31, 2001
Grant Date -
N/A
app pub date -
Feb 1, 2000
filing date -
Feb 1, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
According to one embodiment, a priority encoder (PE)/read-only-memory (ROM) combination circuit (200) includes detect circuits (206-xy) and passgate circuits (208-xy) arranged into rows (202-x) and columns (202-y). Detect circuits (206-xy) of the same column can be activated by a corresponding input signal (M0 to M7). When a detect circuit (206-xy) of a column (202-y) is activated, the passgates (208-xy) of the same column are disabled, preventing any lower priority active input signals (M0 to M7) from propagating further into the circuit.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully