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Abstract

An automatic sampling control system for digital monitors. A clock generation circuit generates a sampling clock. A phase controller modifies the phase of the sampling clock by a phase amount. An ADC samples a frame of an analog display signal to generate digital samples. A value which is a function of the samples is generated. The function generally generates a larger value with correspondingly large sample values. The phase amount is modified for successive image frames until a maximum function value is generated. When successive image frames do not change substantially in image content, the phase amount represents the optimal phase change for the sampling clock. If the image content is changing substantially, the phase adjustment may be disabled.

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