Importance

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Abstract

A cache memory system including a cache memory configured for coupling to a load/store unit of a CPU, a buffer unit coupled to said cache memory, and an operation queue comprising a plurality of entries, wherein each valid operation queue entry points to an entry in the buffer unit. The buffer unit includes a plurality of data buffers and each of the data buffers is associated with a corresponding address tag. The system is configured to initiate a data fetch transaction and allocate an entry in the buffer unit in response to a CPU load operation that misses in both the cache memory and the buffer unit. The cache system is further configured to allocate entries in the operation queue in response to subsequent CPU load operations that miss in the cache memory but hit in the buffer unit prior to completion of the data fetch. Preferably, the system is configured to store the fetched data in the buffer unit entry upon satisfaction of said data fetch and still further configured to satisfy pending load operations in the operation queue from the buffer unit entry. In the preferred embodiment, the system is configured to reload the. cache memory from the buffer unit entry upon satisfying all operation queue entries pointing to the buffer unit entry and, thereafter, to invalidate the buffer unit entry and the operation queue entries. The buffer unit entries preferably each include data valid bits indicative of which portions of data stored in a buffer unit entry are valid.

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First Claim