Importance

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Abstract

A computer system includes a processor, a memory device, at least one expansion bus, and a bridge device coupling the processor, memory device, and expansion bus together. The bridge device preferably includes a memory controller that is capable of arbitrating among pending memory requests, and in certain situations, completing the current cycle after the next cycle begins. This allows executing at least two memory requests concurrently, thus improving bus utilization and retrieving and storing data in memory occurs more efficiently. The memory controller can complete the current memory cycle during the next cycle when the next memory request to be executed will result in a bank miss and a least recently used tracker is currently tracking its maximum number of open memory pages and banks. Further concurrent memory request execution is possible when a bank inactivate condition is valid for the currently executing memory request and the next request to execute will result in a page miss or a page hit to a page other than the MRU page.

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First Claim