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Abstract

A process for forming a vertical, metal-insulator-metal (MIM), capacitor structure, for embedded DRAM devices, using a damascene procedure, has been developed. The process features forming a capacitor opening in a composite insulator layer comprised of a overlying insulator stop layer, a low k insulator layer, and an underlying insulator stop layer, with a lateral recess isotropically formed in the low k insulator layer. After formation of a bottom electrode structure in the capacitor opening, a high k insulator layer is deposited followed by the deposition of a conductive layer, completely filling the capacitor opening. A chemical mechanical polishing procedure is then used to remove portions of the conductive layer, and portions of the high k insulator layer, from the top surface of the overlying insulator stop layer, resulting in the formation of the vertical MIM capacitor structure, in the capacitor opening, comprised of: a top electrode structure, defined from the conductive layer; a capacitor dielectric layer, formed from the high k insulator layer; and a bottom electrode structure.

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First Claim