Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects

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United States of America Patent

PATENT NO 6271087
SERIAL NO

09685968

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Abstract

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A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first photoresist contact mask is deposited, processed, and used to etch core contact and peripheral local interconnect openings. The first photoresist contact mask is removed. A second photoresist contact mask is deposited, processed, and used to etch the multi-layer structures to form local interconnect openings. The second photoresist contact mask is removed. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core contact and peripheral local interconnect openings with core contacts to the source/drain regions and peripheral local interconnect contacts to the multi-layer structures and the source/drain regions.

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Patent Owner(s)

Patent OwnerAddress
MONTEREY RESEARCH LLC3945 FREEDOM CIRCLE SUITE 900 SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hu, YongZhong San Jose, CA 30 344
Kinoshita, Hiroyuki Sunnyvale, CA 185 2398
Sun, Yu Saratoga, CA 426 3781
Wang, Fei San Jose, CA 1116 10607

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