Pipelined memory controller
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United States of America Patent
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Aug 7, 2001
Grant Date -
N/A
app pub date -
Jul 31, 1998
filing date -
Jul 31, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A memory controller which has multiple stages of pipelining. A request buffer is used to hold the memory request from the processor and peripheral devices. The request buffer comprises a set of rotational registers that holds the address, the type of transfer and the count for each request. The pipeline includes a decode stage, a memory address stage, and a data transfer stage. Each stage of the pipeline has a pointer to the request buffer. As each stage completes its processing, a state machine updates the pointer for each of the stages to reference a new memory request which needs to be processed.
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