Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
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United States of America Patent
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Aug 7, 2001
Grant Date -
N/A
app pub date -
Jun 17, 1998
filing date -
Jun 17, 1998
priority date (Note) -
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Abstract
A parallel processing architecture for a digital processor capable of alternately operating in a single threaded mode, a SIMD (single instruction, multiple data) mode and a MIMD (multiple instructions, multiple data) mode. The instruction set for the processor includes instructions for switching between modes and exchanging data between the parallel processing paths. The hardware in any instruction path or portion of an instruction path which is not being used is deactivated to save power.
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