Method for fabricating a low resistance Poly-Si/metal gate

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6277719
SERIAL NO

09439364

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon. A first insulating layer is formed over a silicon substrate, and a polysilicon layer is formed over the first insulating layer. In a key step, the polysilicon layer is annealed to prevent peeling of the subsequently formed diffusion barrier layer. A diffusion barrier layer comprising titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon is formed over the polysilicon layer. A tungsten layer is formed over the diffusion barrier layer, and a capping layer comprising a silicon nitride layer over an oxide layer can be formed over the tungsten layer. The capping layer, the tungsten layer, the diffusion barrier layer, and the first insulating layer are patterned, thereby defining a gate structure.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONHSINCHU

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Randy C H Hsinchu, TW 1 15
Chern, Jin-Dong Hsinchu, TW 4 19
Liaw, Ing-Ruey Hsinchu, TW 36 748
Tsai, Kwong-Jr Chunghsung, TW 6 120

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation