Structure and method for a high performance electronic packaging assembly
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United States of America Patent
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Aug 28, 2001
Grant Date -
N/A
app pub date -
Aug 31, 1998
filing date -
Aug 31, 1998
priority date (Note) -
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Abstract
An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer.
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