Chips arranged in plurality of planes and electrically connected to one another
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United States of America Patent
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-
Aug 28, 2001
Grant Date -
N/A
app pub date -
Apr 22, 1997
filing date -
Jun 28, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged either transverse to the longitudinal extent of the carrier substrate or parallel to the longitudinal extent of the flexibly constructed carrier substrate, as well as a spatial chip arrangement that is formed by means of this process.
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