Circuit and method for reducing parasitic bipolar effects during electrostatic discharges
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United States of America Patent
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Sep 4, 2001
Issued Date -
N/A
app pub date -
Apr 27, 2000
filing date -
Nov 30, 1998
priority date (Note) -
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Abstract
A semiconductor device including a current source having a first node coupled to a terminal, and a second node for extracting a current in response to an electrostatic discharge (ESD) on the terminal. The semiconductor device further including a transistor having a control electrode, a first current electrode coupled to the terminal, and a second current electrode coupled to the second node of the current source, and including a resistive element coupled to a first voltage reference node and the second node of the current source. The transistor of the semiconductor device is biased by detecting a negative voltage event (such as an ESD) at a first current electrode of the transistor and biasing a second current electrode of the transistor in response to detecting the negative voltage event, wherein the biasing of the second current electrode is for preventing a forward biasing of an p-n junction associated with the transistor.
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