Method of defining copper seed layer for selective electroless plating processing
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United States of America Patent
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Sep 11, 2001
Grant Date -
N/A
app pub date -
Jan 4, 1999
filing date -
Jan 4, 1999
priority date (Note) -
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Abstract
A method of manufacturing semiconductor wafers using electroless plating processing. A partially completed semiconductor wafer having trenches and vias formed in a layer of interlayer dielectric has a barrier layer globally formed on the surface of the partially completed semiconductor wafer. A seed layer is globally formed on the surface of the barrier layer. The barrier and seed layers are removed from portions of the surface of the partially completed semiconductor wafer on which plating is not to occur. The partially completed semiconductor wafer is then subjected to an electroless plating process and conductive material is plated on those portions of the seed layer that remains on the partially completed semiconductor wafer.
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