FPGA architecture with deep look-up table RAMs
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United States of America Patent
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Sep 11, 2001
Grant Date -
N/A
app pub date -
May 19, 2000
filing date -
Nov 22, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A configurable logic block (CLB) having a plurality of identical configurable logic element CLE) slices is provided. Each CLE slice includes a plurality of function generators (lookup tables) that can be configured to form a random access memory (RAM). The width and depth of the RAM are selectable by controlling the routing of signals within the CLE slices. A hierarchy of wide function multiplexers (F5, F6, and F7 multiplexers) are provided to selectively route read data values from the lookup tables. Another set of multiplexers is used to selectively route write data values to the lookup tables. These multiplexers can be configured to provide a single write data value to all of the lookup tables to form a deep RAM. Alternatively, these multiplexers can be configured to provide one write data value to half of the lookup tables, and another write data value to the other half of the lookup tables. This pattern repeats down to the level where these multiplexers can be configured to provide a different write data value to each of the lookup tables. A write control circuit is also provided in each CLE slice to provide write enable signals to the lookup tables in a manner consistent with the selected RAM size.
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