System and method for reducing peak current and bandwidth requirements in a display driver circuit
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United States of America Patent
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Sep 11, 2001
Grant Date -
N/A
app pub date -
Nov 14, 1997
filing date -
Nov 14, 1997
priority date (Note) -
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Abstract
A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.
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