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Abstract

A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region and a drain extension are formed from two separate tilted ion implantation processes, after the deposition of the gate electrode. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. A second tilted implant process forms a drain extension region under the gate electrode, adjacent the drain. Elimination of LDD areas reduces the number of masking and doping steps required to manufacture a transistor. Further, the drain extension area promotes transistor performance, by eliminating source resistance. At the same time, sufficient doping of the drain extension area insures that the drain resistance through the drain extension remains low. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. In this manner, larger I.sub.d currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension formed through dual tilted ion implants is also provided.

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First Claim