Importance

Loading Importance Indicators...

Abstract

A field programmable gate array with a matrix of rows and columns of programmable logic cells interconnectable to each other by a network of local and express bus lines and to I/O pads at the perimeter of the logic cell matrix and bus network, is characterized by having a set of reset lines which include main reset lines, column reset lines, and sector reset lines. Each of the main reset lines receives a different reset signal. Each of the column reset lines is associated with a particular column of logic cells of the matrix. Each column reset line is selectively connectable to any one of the main reset lines to receive a selected reset signal. Each of the sector reset lines is connected to a subset of the logic cells in a column. The column reset lines are selective connectable to the logic cells in this respective associated columns by means of the sector reset lines that are connectable to the column reset lines.

Loading the Abstract Image...

First Claim