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Abstract

An integrated circuit device capable of effectively shutting off the power supply in a powerdown mode. The integrated circuit device is connected to a first (ground) power supply, a second power supply that continuously provides power, and a third power supply that halts power supply during the powerdown mode. It includes a controller and a CMOS tri-state driver consisting of a series connection of a P-channel MOS transistor and an N-channel MOS transistor. The P-channel MOS transistor has its source connected to the third power supply, its backgates connected to the second power supply and its gate connected to the controller. The N-channel MOS transistor has its source and backgate connected to the first power supply, its drain connected to the drain of the P-channel MOS transistor and its gate connected to the controller. The controller controls such that the gate of the P-channel MOS transistor is maintained at a high level and the gate of the N-channel MOS transistor is maintained at a low level during the powerdown. Thus, the backgate and the gate of the P-channel MOS transistor are both pulled-up to the high level, thereby keeping the output of the CMOS tri-state driver at a high-impedance state during the powerdown mode. This makes it possible to positively prevent a leakage current, which originates from another CMOS tri-state driver having a common output terminal with the present CMOS tri-state driver, from flowing into the P-channel MOS transistor.

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First Claim