Dual mode bit and gain loading circuit and process
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United States of America Patent
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Sep 18, 2001
Issued Date -
N/A
app pub date -
Feb 22, 2000
filing date -
Dec 16, 1997
priority date (Note) -
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Abstract
A circuit and method that optimizes and adapts the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. A high speed system can select either of a first or a second adaptation routine to handle changes in the bit and gain loadings of sub-channel carriers based on line disturbances or transmission change requests, based on which is most aptly suited to handle the particular change. In a preferred embodiment the resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.
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