Line path determining method and delay estimating method
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United States of America Patent
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Sep 18, 2001
Grant Date -
N/A
app pub date -
Jan 11, 1999
filing date -
Jan 13, 1998
priority date (Note) -
Expired
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Abstract
A line capacitance is estimated in consideration of an influence of an adjacent line in rough routing, so that line paths can be determined so as to be free from a timing error. A routing graph is generated from a target integrated circuit, and line paths of cell-to-cell lines are initially determined on the basis of a passage cost set with regard to each of edges of the routing graph. With regard to each edge of the routing graph, the number of cell-to-cell lines passing through the edge is obtained as a line density, and a line capacitance of each line path in view of the influence of an adjacent line is estimated on the basis of the line density. It is verified whether or not there is a timing error with a delay time estimated, and when the integrated circuit does not satisfy a predetermined timing constraint, the line paths are re-determined with the passage cost of each edge allowed to be affected by the line capacitance. Alternatively, allocation to an interconnect layer is changed or a line-to-line distance is increased, so that the integrated circuit can satisfy the timing constraint.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kurokawa, Keiichi | Hyogo, JP | 37 | 302 |
Yamaguchi, Ryuichi | Osaka, JP | 19 | 199 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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