Method and apparatus for self correcting parallel I/O circuitry
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United States of America Patent
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Sep 25, 2001
Grant Date -
N/A
app pub date -
May 25, 1999
filing date -
May 25, 1999
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Abstract
3An optimal delay value, usually the mid-delay in the operational window, for the data signal may be retained as a way of shifting the skew of the clock on all data lines at the same time. That delay value may be stored in a memory and converted to a control voltage for controlling a digitally controlled voltage variable delay to adjust the delay for data in a bus. The digitally controlled voltage variable delay contains a number of individual delay units which are selectively activated by the control voltage from the value stored in memory. A phase locked loop is employed to ensure that variations due to voltage, temperature, and processing are minimized.
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