Thread switch on blocked load or store using instruction thread field
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United States of America Patent
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Sep 25, 2001
Issued Date -
N/A
app pub date -
Jun 28, 1999
filing date -
Jul 1, 1996
priority date (Note) -
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Abstract
A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.
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